1. Field of the Invention
This invention relates to a power-on reset circuit and more particularly to a circuit for providing a reset pulse signal during initial power supply ramp-up, wherein the circuit operates at low current and is insensitive to changes in power supply slew rate.
2. Description of the Relevant Art
Most power supplies cannot instantly deliver a set (operable) power level to a circuit. Instead, the power supply ramps up power over a period of time, depending upon the load of the circuit. The circuit, therefore, should not become active until the power supply achieves operable power. During ramp-up, the circuit load is generally placed in a reset state and does not operate until after the reset period has passed.
There are many reasons for placing the circuit load in a reset state during power supply initiation. One reason is to ensure that the sequential logic within the circuit load is initialized to a known value. Initializing or "clearing" sequential logic circuits is necessary in order to adequately use those circuits. Another reason for resetting the load circuit is to prevent damage which might be caused by an undervoltage condition. By resetting or halting circuit operation, the load circuit purposefully waits until it receives operation level voltage before it begins operation.
Generation of a reset pulse signal is often achieved by passive and active devices, exemplary such devices are shown in reference to FIG. 1. Specifically, FIG. 1 illustrates a reset pulse signal (V.sub.RST) generated from the active and passive devices and sent to a load circuit 10 which recognizes reset signals. V.sub.RST is driven from an active device 12, such as an amplifier with trigger capability. Active device 12 is stimulated by a biasing current 14. Biasing current 14 is generated through resistor R.sub.1, initially through capacitor C.sub.1 and eventually into active device 12. Accordingly, whenever the power supply (Vcc) ramps from zero voltage or ground to its operational level, biasing current 14 can be considerably high at the initial transient condition through capacitor C.sub.1. If the input impedance on active device 12 is sufficiently low, biasing current 14 can achieve fairly high steady state value. If transients upon the power supply cause Vcc to transition negative, then diode D.sub.1 will become forward biased and provide undervoltage protection.
A problem associated with many conventional reset generating circuits, such as that shown in FIG. 1, is the relatively high biasing current associated with its operation. Biasing current 14 exists not only at transient periods but also can occur and be quite high during steady state through active device 12 and/or load circuit 10. In applications where power consumption must be minimal, it is important that biasing current 14 be as small as possible. In particular, portable devices require that when in standby or non-operation mode, little or no current is drawn by the device. Thus, in situations where the load circuit is, for example, a laptop computer, minimal amounts of bias current 14 exists, and that the bias current which does exist is substantially less than conventional reset generating circuits which use resistor-capacitor passive components.
In addition to their consumption of large amounts of biasing current, conventional reset generating circuits (referred to herein as "power-on reset circuits") are often performance dependent upon the slew rate of the power supply. If, for example, the power supply slew rate is slow, then a possibility exists that the reset signal will terminate prior to the power supply ramping to an operational level. Using FIG. 2 as an illustrative example, two separate slew rates are shown: a fast slew rate 16 and a slow slew rate 18. The faster slew rate 16 is indicative of a faster rate of turn-on of power supply Vcc. The slower slew rate 18 illustrates a slower turn-on rate. Using conventional resistor-capacitor elements, the reset period is timed directly proportional to the resistor and capacitor values. Reset period 20 is of a fixed amount, followed by a non-reset period 22. Reset transitions at an RC time constant of t=R.sub.1 C.sub.1, and that the transition point is the same regardless of the power supply slew rate. If the power supply follows slow slew rate 18, reset is shown to terminate prior to Vcc reaching an operational level V.sub.OP. Thus, slow slew rate 18, which triggers at V.sub.TS, has not yet allowed the power supply to reach operational levels. As a result, the load being driven by the power supply prematurely turns on--leading to improper load operation. If the slew rate is fast, as in curve 16, then the premature turn-on problem is not so severe. In most cases, a fast slew rate power supply will reach operational levels before reset has ended.
The problems of improper operation caused by premature reset transition generally occurs whenever reset transitions are fixed from a defined time constant. The time constant may work well with power supplies having faster slew rates, but are inadequate with power supplies having slower slew rates. From the standpoint of slew rate variability, it would be desirable to redesign the power-on reset circuit to accept variability in power supply slew rates. Additionally, the power-on reset circuit must be redesigned with minimal biasing current during transition periods and during periods of steady state.